It would be interesting to do a write-up like this on "modern microcontrollers." Some of the content is similar (some µc cores look relatively similar to µp cores with a 10-20 year lag), but there's differences too. Things that would come to mind for me:
1) Strategic pipeline lengths -- long pipelines drive throughput, short pipelines drive interrupt responsiveness. 5-stage pipelines are still popular for realtime cores.
2) Heterogenous cores -- a mix of short- and long-pipeline cores on a single chip, with some optimized for responsiveness and some optimized for throughput. (This could actually be added to the µp article as well, discussing big.LITTLE style heterogeneity with some cores optimized for total throughput and some optimized for power efficiency.) Unlike in the µp case, this is pared with a general assumption that cores are usually developer-managed (asymmetric multiprocessing) rather than magically managed by a scheduled (symmetric multiprocessing). (Dedicated cores for low power come up in µcs too.)
3) Fast memories; some very fast memories. Everything fits in SRAM on chip. Some SRAM is tightly coupled to a specific core (tightly coupled memory), which gives as fast as single cycle access; some is hanging off an AXI bus to allow sharing between cores, but adds a few cycles (and possible collisions) to access, making caches still relevant (which has not always been true for µcs). The µp developer approach to performance of "memory accesses rule everything" is not nearly as true on µcs.
4) Peripherals and accelerators dominate silicon area, and dominate system performance. (This can also be said of µps these days.) Proper use of DMA engines can completely change the solution to problems. Smart peripherals unload huge amounts of work from the core, making the core less important -- in some cases, it's really just there to configure the DMA engine and the peripherals. (This sounds an awful lot like cores on a µp just feeding GPUs these days.)
5) Topology awareness. Multiple AXI busses and peripheral busses; software needs to be aware of what peripheral or SRAM chunk hangs off what bus to maximize performance, minimize collisions, or even just to allow the peripheral to be used at all from a given core in a given power state. This has some similarities to NUMA awareness in µp development, but as with AMP vs SMP it's generally more visible to developers.
This is the kind of website that needs to come back! No "cookies bs", ads everywhere, "plz sign up to my mailing list", "share your location", "comment where are you from", "buy my ebook", subscribe, share.
It really hurts to see what a dumpster fire the internet of today is compared to the 90s or even the Web 2.0 days. There are some things we have now like Anna's Archive that are gems, and I'm sure a number of other hidden gems out there I don't even know about, but it's buried in all the noise. The Big Tech sites have infested and taken over everything and ruined it all, and the masses are happy to go along for the ride. I would argue that Eternal September was not an isolated event but a sneak preview of the Hell to come, like the beginning of a tidal wave when the first part surges in.
I'm still waiting for the update that explains why, after going from clock speed to FLOPS, etc. (which I understood) we suddenly started measuring processing power in GW. It makes as much sense as measuring automotive motors in decibels.
Speaking in terms of GW makes sense when we are discussing performance of an individual datacenter since power is, kind of, the limiting factor.
Also, FLOPs per watt hasn't changed as much lately, so thinking in terms of watts over a few-year time horizon does at least give you a ballpark of how many FLOPs.
If you're talking about a chip, you obviously want to know about FLOPs moreso, but, even down to the level of individual rack-units, wattage is a serious concern. Not every facility is built for these crazy 200kW racks.
Yeah, I get that. But using something that should be on the "costs" side of the ledger as your metric still seems fraught. It feels like another LOC trap.
It would be interesting to do a write-up like this on "modern microcontrollers." Some of the content is similar (some µc cores look relatively similar to µp cores with a 10-20 year lag), but there's differences too. Things that would come to mind for me:
1) Strategic pipeline lengths -- long pipelines drive throughput, short pipelines drive interrupt responsiveness. 5-stage pipelines are still popular for realtime cores.
2) Heterogenous cores -- a mix of short- and long-pipeline cores on a single chip, with some optimized for responsiveness and some optimized for throughput. (This could actually be added to the µp article as well, discussing big.LITTLE style heterogeneity with some cores optimized for total throughput and some optimized for power efficiency.) Unlike in the µp case, this is pared with a general assumption that cores are usually developer-managed (asymmetric multiprocessing) rather than magically managed by a scheduled (symmetric multiprocessing). (Dedicated cores for low power come up in µcs too.)
3) Fast memories; some very fast memories. Everything fits in SRAM on chip. Some SRAM is tightly coupled to a specific core (tightly coupled memory), which gives as fast as single cycle access; some is hanging off an AXI bus to allow sharing between cores, but adds a few cycles (and possible collisions) to access, making caches still relevant (which has not always been true for µcs). The µp developer approach to performance of "memory accesses rule everything" is not nearly as true on µcs.
4) Peripherals and accelerators dominate silicon area, and dominate system performance. (This can also be said of µps these days.) Proper use of DMA engines can completely change the solution to problems. Smart peripherals unload huge amounts of work from the core, making the core less important -- in some cases, it's really just there to configure the DMA engine and the peripherals. (This sounds an awful lot like cores on a µp just feeding GPUs these days.)
5) Topology awareness. Multiple AXI busses and peripheral busses; software needs to be aware of what peripheral or SRAM chunk hangs off what bus to maximize performance, minimize collisions, or even just to allow the peripheral to be used at all from a given core in a given power state. This has some similarities to NUMA awareness in µp development, but as with AMP vs SMP it's generally more visible to developers.
I could keep going... there's an article here.
Great article.
Wish list of topics to add:
- branch predictors that can detect patterns (edit: I guess it's already covered in the paragraph about raising prediction accuracy)
- LRU-approximations in L1 caches
- Data prefetching (sequential, stride)
- Return address stack
Concerning μops, I think the 68060 did that, too.
This is the kind of website that needs to come back! No "cookies bs", ads everywhere, "plz sign up to my mailing list", "share your location", "comment where are you from", "buy my ebook", subscribe, share.
I've recently come across a language learning website that was nothing but HTML and a very light bit of CSS. It was beautiful.
link?
I should specify, it was explicitly for Hungarian.
Ah, HungarianText Markup Language.
I meant the website. It's http://www.hungarianreference.com.
Still has a gigantic blocking ad on mobile
Who isn't using an adblocker these days?
If everyone's using an adblocker, then why are ads that no one is seeing being served?
… and full of page-turning information! That was a really interesting read :)
You forgot notifications
It really hurts to see what a dumpster fire the internet of today is compared to the 90s or even the Web 2.0 days. There are some things we have now like Anna's Archive that are gems, and I'm sure a number of other hidden gems out there I don't even know about, but it's buried in all the noise. The Big Tech sites have infested and taken over everything and ruined it all, and the masses are happy to go along for the ride. I would argue that Eternal September was not an isolated event but a sneak preview of the Hell to come, like the beginning of a tidal wave when the first part surges in.
I'm still waiting for the update that explains why, after going from clock speed to FLOPS, etc. (which I understood) we suddenly started measuring processing power in GW. It makes as much sense as measuring automotive motors in decibels.
Speaking in terms of GW makes sense when we are discussing performance of an individual datacenter since power is, kind of, the limiting factor.
Also, FLOPs per watt hasn't changed as much lately, so thinking in terms of watts over a few-year time horizon does at least give you a ballpark of how many FLOPs.
If you're talking about a chip, you obviously want to know about FLOPs moreso, but, even down to the level of individual rack-units, wattage is a serious concern. Not every facility is built for these crazy 200kW racks.
Yeah, I get that. But using something that should be on the "costs" side of the ledger as your metric still seems fraught. It feels like another LOC trap.
Previously...
Modern Microprocessors – A 90-Minute Guide (2001-2016) - https://news.ycombinator.com/item?id=27014027 - May 2021 (41 comments)
Modern Microprocessors – A 90-Minute Guide (2001-2016) - https://news.ycombinator.com/item?id=18230383 - Oct 2018 (87 comments)
Modern Microprocessors – A 90 Minute Guide - https://news.ycombinator.com/item?id=11116211 - Feb 2016 (12 comments)
Modern Microprocessors: A 90 Minute Guide - https://news.ycombinator.com/item?id=7174513 - Feb 2014 (37 comments)
Modern Microprocessors: A 90 Minute Guide - https://news.ycombinator.com/item?id=2428403 - April 2011 (30 comments)
according to the title, I believe this should link here: https://www.lighterra.com/papers/modernmicroprocessors/
Fixed, thanks!
[flagged]